| 摘要 |
A test circuit for measuring the delay of a signal through a manufactured integrated circuit in order to find discrepancies between simulation models corresponding to the used manufacturing process and the process itself, comprises a delay circuit (DLY). The simulation models of the delay circuit (DLY) are used to predetermine maximum and minimum allowable delays of a pulse edge supplied to the input terminal of the delay circuit. A first verifying circuit (4, 5, 6) connected to the output terminal of the delay circuit (DLY) verifies whether or not the delay of the pulse edge is above this predetermined minimum value. A second verifying circuit (7, 8, 9, DLYC, DLYS) connected to the output terminal of the delay circuit (DLY) verifies whether or not the delay of the pulse edge is below this predetermined maximum value.
|
