| 摘要 |
An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc., onto a bus together with a data transfer request without involving use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to the state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.
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