| 摘要 |
PURPOSE: A circuit for generating a jamming signal in a jamming responder is provided to be simplified by generating synchronous and asynchronous control signals for transmitting a control signal and jamming data to a DTO and each RF(Radio Frequency) switch and unifying a variable storing unit and a real-time control unit as one system. CONSTITUTION: A priority control circuit(111) outputs a synchronous threat signal and a real-time synchronous signal corresponding to a high priority among a plurality of output control signals inputted from a TRK/TG. An asynchronous time division control circuit(112) receives a channel selection signal inputted from a jamming control circuit and outputs an asynchronous time division sequential signal and a channel number for selecting a specific channel. A threat signal generating circuit(113) receives the signal outputted from the asynchronous time division control circuit(112) and generates an asynchronous threat signal of a corresponding channel. A DPM output control/DTO 1, 2 control signal generating circuit(114) receives each signal outputted from the priority control circuit(111), the asynchronous time division control circuit(112), and the threat signal generating circuit(113), controls a priority between synchronization and asynchronization, and outputs a threat signal and a DTO 1, 2 latch signal to a stamp generating circuit according to the priority. The DPM output control/DTO 1, 2 control signal generating circuit(114) outputs a signal in which the DTO 1, 2 switch signal and the synchronous and asynchronous control signals are added to the jamming control circuit, processes synchronous and asynchronous priorities, and outputs a corresponding threat signal and a memory control signal. A dual port RAM(122) outputs a frequency of the corresponding threat signal, a jamming bandwidth, and jamming type data according to a memory control signal inputted from the outside. A decoder and memory control circuit(121) receives a corresponding threat-classified jamming variable according to the control signal inputted from the jamming control circuit, and generates a write signal and a read signal for storing the received variable in the dual port RAM(122) and reading data from the dual port RAM(122). The decoder and memory control circuit(121) receives data from the TRK/TG and confirms whether the received data are PF(Predicted Frequency) data, divides addresses and data, and stores the divided addresses and data in the dual port RAM(122). The decoder and memory control circuit(121) receives the threat signal and an output enable signal outputted from the DPM output control/DTO 1, 2 control signal generating circuit(114), generates a memory control signal for outputting corresponding data, and outputs the generated memory control signal. |
