发明名称 |
Stacked integrated circuit and capacitor structure containing via structures |
摘要 |
An integrated circuit structure includes a planar capacitor positioned adjacent to a logic circuit implemented on a silicon die. The silicon die is bonded to a mounting base using controlled collapse chip connection methods such that a ground terminal of the silicon die is coupled to a ground trace in the mounting base and a Vdd terminal of the silicon die is coupled to a Vdd trace in the mounting base. The capacitor includes via structures with controlled collapse chip connection structures for bonding to the mounting base directly above the silicon die and coupling a first charge accumulation plate to the Vdd trace and a second charge accumulation plate to the ground trace. |
申请公布号 |
US6452250(B1) |
申请公布日期 |
2002.09.17 |
申请号 |
US20000488289 |
申请日期 |
2000.01.20 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
BUYNOSKI MATTHEW S. |
分类号 |
H01G2/06;H01L23/498;(IPC1-7):H01L29/00 |
主分类号 |
H01G2/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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