发明名称 |
Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual |
摘要 |
The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.
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申请公布号 |
US6451647(B1) |
申请公布日期 |
2002.09.17 |
申请号 |
US20020100819 |
申请日期 |
2002.03.18 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
YANG CHIH-YUH;NGO MINH VAN |
分类号 |
H01L21/28;H01L21/311;H01L21/3213;H01L29/51;(IPC1-7):H01L21/824;H01L21/108;H01L21/20;H01L21/302;H01L21/31 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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