| 摘要 |
A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge. In another embodiment, the RAM cells are arranged in a loop so that the sequence of RAM cells forms a ring oscillator, the period of which provides an indication of the time required for the RAM cells to store data in response to clock edges.
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