| 摘要 |
Disclosed herein is an edge enhancement circuit which is capable of reducing required memory capacity and power consumption. An input analog video signal HVa is sampled based on a clock signal CLKH1, to obtain a digital video signal HVb. An edge-enhanced signal HIEa is obtained by a filter operation using the video signal HVb and its delayed signals HVc and HVd. The video signal HVa is sampled based on a clock signal CLKH2 kept in inverse phase with the clock signal CLKH1 to obtain a digital video signal HVe, after which its delayed signal HVf is obtained. Pixel data constituting the video signals HVf and HVc are alternately taken out based on a clock signal CLKH3 having a frequency corresponding to that of the clock signal CLKH1 to obtain a main-line signal HVg. The main-line signal HVg and edge-enhanced signal HIEa are respectively converted to analog signals, which in turn are added together to obtain an edge-enhanced output analog video signal HVi. Pixel data for obtaining the edge-enhanced signal are set at one-pixel intervals with respect to that about the main-line signal.
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