| 摘要 |
A non-volatile memory device includes an array of non-volatile memory cells. The memory has control circuitry to apply erase voltage pulses to the non-volatile memory cells and perform erase verification operations. A pulse counter is coupled to count the erase pulses applied to the non-volatile memory cells. A programmable erase pulse register has been described that indicate a number of initial erase pulses that can be applied to the non-volatile memory cells during an initial verification operation prior to performing a scan operation of the memory block. The control circuitry can also apply additional erase pulses following subsequent erase verification operations. A second programmable erase pulse register is provided to indicate a number of subsequent erase pulses that can be applied to the non-volatile memory cells before performing additional scan operations.
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