| 摘要 |
A memory controller providing a synchronous SRAM interface to an embedd ed DRAM is disclosed. To achieve maximum performance DRAM timing, control logic is emulated in the controller to produce DRAM control signals. Control signal timing can be flexibly adjusted using control registers. The memory controller's interface and the DRAM's interface operate in separate clock domains. In other words, since the timin g of DRAM control signals is asynchronous from the interface clock and based on the embedded DRAM timing emulation, all margins can be minimized. The SRAM interface can opera te in a wide range of clock frequencies, which are not restricted to ratios of multiples of the embedded DRAM clock frequency. The controller produces the DRAM clock signal asynchronously with respect to the interface clock. Therefore improved DRAM performance is achieved without modifying the embedded DRAM logic, to improve performance of the system in which the DRAM is embedded within.
|
