| 摘要 |
PURPOSE: A CMOS TFT having an offset region and a method for fabricating the same are provided to simplify a fabrication process by reducing the number of mask and improve characteristics of by reducing leakage current in an off state. CONSTITUTION: A buffer layer(41) is formed on a substrate(40). A polysilicon layer is formed on the buffer layer(41). The first mask is formed on the polysilicon layer. Polysilicon layer patterns(42a,42b) are formed on an N type TFT region(40a) and a P type TFT region(40b), respectively. A gate insulating layer, a gate electrode material, and a capping layer are formed sequentially on the buffer layer(41). The second mask layer is formed on the capping layer including the polysilicon layers(42a,42b). A gate electrode(44a) of an N type TFT is formed by patterning the capping layer and the gate electrode material. An insulating layer is formed on a whole surface of the substrate(40). A spacer(47a) is formed on a sidewall of the gate electrode(44a) and a sidewall of the gate electrode material. A high density source/drain region(48) of an N type TFT is formed on the polysilicon layer(42a). The third mask is formed on the substrate(40). A gate electrode(44b) of the P type TFT is formed on the third mask. A high density source/drain region(51) is formed by implanting P type dopants of high density. Gate electrodes(44a,44b) of the N type and the P type TFTs are formed by forming and etching an insulating layer(52). Spacers(52b) are formed on sidewalls of capping layers(45a,45b). A source/drain electrode(53a) of the N type TFT and a source/drain electrode(53b) of the P type TFT are formed by etching the fourth mask.
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