发明名称 |
CLOCK-SKEW RESISTANT CHAIN OF SEQUENTIAL CELLS |
摘要 |
In an integrated circuit incorporating a series of sequential cells (SEQ(1)-SEQ(7)) implementing a shift function, clock skew problems are avoided by interconnecting the cells in order starting with the cell (SEQ(3)) having greatest clock latency and ending with the cell (SEQ(7)) having smallest clock latency. |
申请公布号 |
WO02071411(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
WO2002IB00511 |
申请日期 |
2002.02.20 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
NATALI, FREDERIC;SOUEF, LAURENT |
分类号 |
G01R31/317;G01R31/3185;G11C19/00 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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