发明名称 |
METHOD AND APPARATUS FOR ADJUSTING THE CLOCK DELAY IN SYSTEMS WITH MULTIPLE INTEGRATED CIRCUITS |
摘要 |
An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.
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申请公布号 |
WO02071682(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
WO2002US06526 |
申请日期 |
2002.03.04 |
申请人 |
GENERAL DYNAMICS GOVERNMENT SYSTEMS CORPORATION |
发明人 |
ZAK, JOAN, E.;DENNY, RONALD, R.;SIMON, CHRIS, H. |
分类号 |
G06F1/10;H03L7/081;(IPC1-7):H04L7/00;H04L25/05;H04L25/40 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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