SPLIT COMMON SOURCE ON EEPROM ARRAY

摘要

An EEPROM having reduced circuit loading of a high voltage write pulse by dividing an array of bit cells into two or more switchable common source segments. Only common source segments containing the bit cells being written to are connected, the other common source segments remain unconnected and do not contribute substantially to loading of the write pulse. Having multiple switchable common segmentations reduces the amount of parasitic capacitance connected in the EEPROM array during a write operation, thus reducing lading on the write circuits. Also reducing the number of bit cells having the common source segments connected during a write operation reduces the amount of leakage current contribution which adversely affects the write operation.