发明名称 |
A method of testing an integrated circuit on a functional block by functional block basis |
摘要 |
A design for testability is applied so as to enable significant reduction in test time of an actual integrated circuit. First, an integrated circuit is full-scan designed on a block-by-block basis and test input patterns are generated (S11). Then, one of the blocks to which the design for testability has not been allocated is selected (S12), and a full-scan design is allocated thereto (S14). Test points are inserted into a block that has more than a prescribed number of parallel test input patterns when that block is full-scan designed (YES in S15) (S16).
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申请公布号 |
US2002129322(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
US20010789524 |
申请日期 |
2001.02.22 |
申请人 |
HOSOKAWA TOSHINORI;YOSHIMURA MASAYOSHI |
发明人 |
HOSOKAWA TOSHINORI;YOSHIMURA MASAYOSHI |
分类号 |
G01R31/28;G01R31/3181;G01R31/3183;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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