| 发明名称 |
DATA PROCESSING APPARATUS AND SYSTEM AND METHOD FOR CONTROLLING MEMORY ACCESS |
| 摘要 |
A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements. |
| 申请公布号 |
CA2478570(A1) |
申请公布日期 |
2002.09.12 |
| 申请号 |
CA20022478570 |
申请日期 |
2002.03.04 |
| 申请人 |
ATSANA SEMICONDUCTOR CORP. |
发明人 |
LE, THINH M.;HO, TUAN;GIERNALCZYK, ERIC;STEWART, ANDREW;STEWART, MALCOM;NITA, ADRIAN G.;WONG, DENNY |
| 分类号 |
G06F3/00;G06F7/575;G06F9/302;G06F13/16;G06F15/173;G06F15/80;(IPC1-7):G06F13/42 |
主分类号 |
G06F3/00 |
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