发明名称 DELAY LOCK LOOPS FOR WIRELESS COMMUNICATION SYSTEMS
摘要 Techniques for deriving sample timing for multiple signal instances received on multiple antennas for a given propagation path. In one scheme, a DLL is maintained for each path, and each DLL tracks the timing of the best signal instance for the assigned path. In another scheme, a DLL is maintained for each path, and each DLL tracks the average timing of the multiple signal instances for the assigned path. To reduce timing jitter, the SINR of a signal instance may be estimated for a number of different time offsets. The loop filter for the DLL is initially updated in the normal manner. If a change in the time offset used for the sample timing is detected, then the SINRs for the new and prior offsets are compared. The new time offset is used if the associated SINR is better. Otherwise, the prior time offset is retained and used.
申请公布号 WO02071647(A1) 申请公布日期 2002.09.12
申请号 WO2002US01793 申请日期 2002.01.17
申请人 QUALCOMM INCORPORATED 发明人 BLACK, PETER, J.;SINDHUSHAYANA, NAGABHUSHANA, T.
分类号 H04B1/707;H03L7/089;H03L7/091;H03L7/093;H04B7/08;(IPC1-7):H04B7/08 主分类号 H04B1/707
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