HIGH-SPEED MOS SENSE AMPLIFIER

摘要

An improved sense amplifier comprised of an all FET amplifying circuit having means for limiting the voltage swing of the read potential applied thereby to an integrated circuit memory array in sensing the stored "1" and "0" memory states. The amplifier includes upper and lower output level-limiting circuits which detect predetermined signal levels in the output signal of the amplifier and cause the impedances at the input of the amplifier to be adjusted to limit the output signal swing of the amplifier to within the predetermined signal leads. In so doing, the memory read potential is also constrained to swing within certain predetermined limits.