| 摘要 |
Process for interconnecting between data processing or data communication modules (A and B) by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. It consists, on transmission and on reception, of performing an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and of digitally synchronizing the start-of-frame of each slave module to the start-of-frame sent by the master module. The invention applies especially to the interconnection of multiprocessor modules by point-to-point serial-to-parallel links.
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