发明名称 |
Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs |
摘要 |
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.
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申请公布号 |
US2002126560(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
US20020043683 |
申请日期 |
2002.01.10 |
申请人 |
COWLES TIMOTHY B.;SHORE MICHAEL A.;MULLARKEY PATRICK J. |
发明人 |
COWLES TIMOTHY B.;SHORE MICHAEL A.;MULLARKEY PATRICK J. |
分类号 |
G11C7/10;G11C11/406;(IPC1-7):G11C5/02 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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