发明名称 Reset facility for redundant processor using a fibre channel loop
摘要 A processor resetting apparatus comprises a fibre channel arbitrated loop (FC-AL) interface arranged to receive a frame over the FC-AL containing an indicator of a reset command for a server comprising one of a redundant pair of servers and including a processor associated with the resetting apparatus. The apparatus further comprises a reset component, responsive to the reset command, to issue a reset command for resetting the processor. The apparatus therefore provides the ability for a server to reset another server if it detects that the server is faulty.
申请公布号 US2002129232(A1) 申请公布日期 2002.09.12
申请号 US20020091647 申请日期 2002.03.05
申请人 COFFEY AEDAN DIARMUID CAILEAN 发明人 COFFEY AEDAN DIARMUID CAILEAN
分类号 G06F1/24;H04L12/42;H04L29/06;H04L29/08;H04L29/14;(IPC1-7):G06F15/177;G06F9/24;G06F9/00 主分类号 G06F1/24
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