Semiconductor integrated circuit device including a cache having a comparator and a memory

摘要

A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.