发明名称 APPARATUS FOR VARIABLE WORD LENGTH COMPUTING IN AN ARRAY PROCESSOR
摘要 <p>A computational unit comprises a processor having a plurality of processing elements, each having an arithmetic logic unit, and a controller for controlling the processor elements. The processor can provide a respectivef bit of a multiple bit word to each of the processor elements and enables signals to be transmitted between the arithmetic logic units to enable the units to perform a parallel operation on the bits of the multiple bit word. Extension circuitry is provided for selectively coupling one or more computational units together to combine their parallel processing capability.</p>
申请公布号 WO2002071240(A2) 申请公布日期 2002.09.12
申请号 CA2002000279 申请日期 2002.03.04
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