发明名称 METHOD FOR FORMING FINE PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To form a fine pattern having both of a groove pattern and a hole pattern in the process of manufacturing a semiconductor device without carrying out vacuum vapor deposition. SOLUTION: A two-layer resist having an organic resin 13 as the lower layer resist and a silylation resist 14 as the upper layer resist is formed by coating. A part of the silylation resist 14 is exposed in a hole pattern (a cylindrical form) and crosslinked, then the whole surface of the wafer is silylated to add Si in the part except for the crosslinked part 15 of the upper layer resist. After the upper layer resist is subjected to the treatment to improve the heat resistance, a two-layer resist having an organic resin 19 as the lower layer resist and a silylation resist 20 as the upper layer resist is further formed thereon by coating. The part of the silylation resist 20 corresponding to the position above the crosslinked part 15 is crosslinked in a groove pattern (in a parallelepiped form), and then the whole surface of the wafer is silylated. The wafer is finally etched to form a groove pattern 23 and a hole pattern 24.
申请公布号 JP2002258493(A) 申请公布日期 2002.09.11
申请号 JP20010059930 申请日期 2001.03.05
申请人 SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC 发明人 SATO ISAO
分类号 G03F7/38;H01L21/027;H01L21/3205;(IPC1-7):G03F7/38;H01L21/320 主分类号 G03F7/38
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