| 摘要 |
The present invention provides a method and apparatus for determining the RC delays of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. The rules checker algorithm operates in conjunction with a static timing analyzer. The static timing analyzer reads a netlist. The rules checker algorithm utilizes information relating to the netlist to generate a Spice deck which defines a circuit to be simulated. In the Spice deck, the driver gates of the network are replaced with ramp function voltage sources. The Spice deck includes the parasitic resistances and capacitance associated with the network. Once the Spice deck has been generated, the rules checker program calls a Spice simulation routine, which simulates the circuit defined by the Spice deck. The Spice routine generates a Spice results file that comprises voltage waveform information relating to the simulation. The rules checker algorithm utilizes this waveform information to determine the RC delays of the network. The determined RC delays may be utilized to determine whether or not the network meets maximum allowable RC delay specifications.
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