| 摘要 |
A comparator circuit that transforms a difference between two input voltage signals into differential branch currents that are independent of the two input voltage signals. In one embodiment, the comparator circuit utilizes an adaptive bias voltage circuit and a cascode stage to generate the differential branch currents that are applied to a conventional CMOS latch. The adaptive bias voltage circuit utilizes a current source and the two input voltages to generate a bias voltage that is directly proportional to an average of the two input voltage signals. The cascode stage includes two parallel branches, each including an n-channel transistor connected in series with a p-channel transistor between the CMOS latch and ground. The bias signal is applied to the gate terminals of the n-channel transistors of both branches, and the two input voltages are respectively applied to the gate terminals of the p-channel transistors of the branches.
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