| 摘要 |
A clock-recovery system is used to align a clock-phase with the RGB-signals. A frequency-synthesizing loop is applied for receiving a reference clock signal (CKREF) to generate a synthesized frequency. A fine-tuned frequency-synthesizing loop then receives a horizontal synchronization signal (HSYNC) to fine-tune the synthesized frequency into a fine-tuned synthesized frequency. A phase divider subdivides the fine-tuned synthesized frequency into a multiple phase segments for inputting to a multiplex controller. An analog sensor, receives and senses the RGB signals for generating encoded sensing data corresponding to voltage transitions of the RGB signals. A transition detector then applies the encoded sensing data for generating transition-detection data. A threshold triggering circuit compares the transition-detection data with a threshold data and triggering a RGB-phase data upon detecting the threshold data is exceeded by the transition detection data. A phase sampling detector applies the RGB-phase data for selecting a clock-alignment phase-segment from one of the multiple phase segments received from the multiplex controller for aligning the clock-phase. A digital phase-lock loop (PLL) includes a phase shift-direction detector (PD) receives the RGB-phase data from the threshold triggering circuit and the clock-alignment phase-segment from the multiplex controller for generating a dynamic phase-shift difference. The digital PLL further includes a digital filter to receive the dynamic phase-shift difference from the PD for generating a phase-segment-shift signal for outputting to the multiplex controller for shifting the clock-alignment phase-segment to dynamically align the clock-phase.
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