| 摘要 |
Disclosed is a method for fabricating a semiconductor device including stacked capacitors, in which dummy plate electrodes and charge storage electrodes are formed at a region other than a memory cell region, to control a topology resulting from capacitors, thereby allowing fine interconnection lines to be formed after the formation of those capacitors. In accordance with this method, dummy plate electrodes and charge storage electrodes, each of which has the same height as that of the stacked capacitor, are formed at the logic circuit region when the stacked capacitor are formed at the memory cell region.
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