| 摘要 |
PURPOSE: A method for fabricating a semiconductor memory device having a cell node plug is provided to improve reliability and yield by basically preventing cell node plugs from being short-circuited by shortage of a process margin, and to control the line width of a word line by controlling the thickness of a spacer on the sidewall of the cell node plug. CONSTITUTION: An isolation layer is formed on a semiconductor substrate to define an active region. The first conductive layer for the cell node plug is formed on the resultant structure. The first conductive layer on the isolation layer is selectively eliminated and the gap is filled with the first insulation layer. The first conductive layer and the first insulation layer are selectively removed to form a groove exposing the semiconductor substrate in a word line formation region. The first spacer insulation layer is formed on the sidewall of the groove. A gate insulation layer is formed on the exposed semiconductor substrate. The second conductive layer is filled in the groove to form the word line.
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