发明名称 Method of forming a via overlap
摘要 Briefly, in accordance with one embodiment of the invention, a method of forming at least two vias, each having a metal overlap, to interconnect at least two connection points with metallization includes the following. The at least two vias are etched through a layer of insulating material. The at least two etched vias are located diagonally with respect to one another. Metal overlap for each of the at least two vias is formed into a polygon shape having more than four sides.Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium, the storage medium having stored thereon, instructions, which, when executed, result in: the placement and routing of vias between at least two connection points to be interconnected with metallization by positioning at least two vias diagonally with respect to one another, the at least two vias being positioned so each is capable of having a polygon shape of metal overlap with more than four sides.Briefly, in accordance with still another embodiment of the invention, an integrated cicuit includes: a semiconductor substrate, the semiconductor substrate having formed thereon an interconnect. The interconnect including at least two vias, the at least two vias being located diagonally with respect to one another and each having a metal overlap with a polygon shape of more than four sides.
申请公布号 US6446873(B1) 申请公布日期 2002.09.10
申请号 US20000693533D 申请日期 2000.10.20
申请人 INTEL CORPORATION 发明人 GERYK NATHAN
分类号 H01L23/522;(IPC1-7):G06K19/00 主分类号 H01L23/522
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