发明名称 Time division multiplexed synchronous state machine having state memory
摘要 An implementation of a synchronous state machine, responsive to a time division multiplexed external input signal having plural time slots in a repetitive structure, has all of its flip-flop outputs hooked up to a state memory so that the state produced by each time slot is stored until that time slot is again repeated at the external input, at which point the stored state is recalled from memory for being input along with the incoming time slot data; in this way the hardware is shared between time slots. A substitution element is disclosed having a flip-flop with its output routed to memory and for providing a memory output as its output. A design methodology is taught whereby a state memory and a substitution element is substituted for each flip-flop in a synchronous state machine implemented for one time slot of a repeating pattern of time slots.
申请公布号 US6449292(B1) 申请公布日期 2002.09.10
申请号 US19970924451 申请日期 1997.08.28
申请人 ALCATEL 发明人 WEEBER WILLIAM B.
分类号 H04J3/06;(IPC1-7):H04J3/06 主分类号 H04J3/06
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