发明名称 Multi-processor bus protocol system
摘要 A method of communicating between first and second controllers (including between processes within the controllers, or microprocessors) on an I2C bus is provided. The I2C bus is of the type which transmits data packets that start with a start condition and end with a stop condition, and that includes a destination address followed by a transmission type, a first data byte, a second data byte, and one or more additional data bytes. The method includes the steps of: designating a destination address with a unique bus address (i.e., devAddress) of the second controller; designating the first data byte with a unique bus address (i.e., ownAddress) of the first controller; and specifying the transmission type, wherein the first and second controllers initiate a master-slave relationship for read and write operations between controllers. The invention also provides an I2C bus protocol system. The system includes an I2C bus with means for communicating an I2C packet across the bus. First and second controllers connect to the bus, with each controller having (a) means for specifying a devAddress as a slave address in the I2C packet, (b) means for specifying ownAddress as a master address in a first data byte of the I2C packet, and (c) means for specifying a tag within a subsequent data byte of the I2C packet, wherein the first and second controllers initiate a master-slave relationship for read and write operations along a conduit between processes within the controllers.
申请公布号 US6449289(B1) 申请公布日期 2002.09.10
申请号 US19980169444 申请日期 1998.10.09
申请人 ADAPTEC, INC. 发明人 QUICKSALL EDWARD S.
分类号 G06F13/42;(IPC1-7):G06F13/16 主分类号 G06F13/42
代理机构 代理人
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