发明名称 Low hold time statisized dynamic flip-flop
摘要 A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.
申请公布号 US6448829(B1) 申请公布日期 2002.09.10
申请号 US20010876765 申请日期 2001.06.07
申请人 SUN MICROSYSTEMS, INC. 发明人 SARAF RITESH
分类号 H03K3/012;H03K3/356;H03K3/3562;(IPC1-7):H03K3/12 主分类号 H03K3/012
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