发明名称 Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode
摘要 An EEPROM is incorporated in a single chip microcomputer for storing programmed instruction codes, and is tested before separation of a semiconductor wafer into semiconductor chips, wherein pads used in the EEPROM test are arranged along an edge of the semiconductor chip so as to permit an external tester to concurrently bring two rows of probes into contact therewith, thereby improving the testability.
申请公布号 US6449740(B1) 申请公布日期 2002.09.10
申请号 US19990365909 申请日期 1999.08.03
申请人 NEC CORPORATION 发明人 YOSHIE TAKEO
分类号 G06F11/22;G06F11/26;G06F15/78;G11C29/00;(IPC1-7):G06F11/26 主分类号 G06F11/22
代理机构 代理人
主权项
地址