Method and device structure for enhanced ESD performance

摘要

An integrated circuit manufacturing process selectively blocks silicide formation during the fabrication of I/O devices to enhance their ESD performance while not impacting the performance of core devices. In an example embodiment, a spacer dielectric covers the MOS structure so that the gate may be protected from process degradation. The spacer dielectric is masked to define silicidation blocking regions and silicidation accepting regions. Spacer dielectric is removed in regions where silicidation is to be accepted. Silicidation blocking regions protect transistor devices from subsequent ion implantation. Consequently, the ion implantation profiles for core transistors and I/O transistors are maintained for enhanced performance and reliability for each transistor type.