发明名称 |
Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions |
摘要 |
A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes "prepare to branch" instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.
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申请公布号 |
US6449712(B1) |
申请公布日期 |
2002.09.10 |
申请号 |
US19990410851 |
申请日期 |
1999.10.01 |
申请人 |
HITACHI, LTD. |
发明人 |
IRIE NAOHIKO;WERNER TONY LEE;PENG CHIH-JUI;ZIESLER SEBASTIAN H.;FREEMAN JACKIE A.;KRISHNAN SIVARAM |
分类号 |
G06F9/30;G06F9/318;G06F9/32;G06F9/38;(IPC1-7):G06F9/455 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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