LOW LATENCY MEMORAY SYSTEM ACCESS

摘要

A low latency memory system access is provided in association with a weakly- ordered multiprocessor system(Fig.1). Each processor(12-1, 12-2) in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device(10) that provides support for synchronization between the multiple processors(12-1, 12-2) in the multiprocessor and the orderly sharing of the resources. A processor(12-1, 12-2) only has permissio n to access a resource when it owns the lock associated with that resource, an d an attempt by a processor(12-1, 12-2) to own a l ock requires only a single load operation, rather than a traditional atomic load followed by store, suc h that the processor(12-1, 12-2) only performs a read operation and the hardwa re locking device(10) performs a subsequent write operation rather than the processor(12-1, 12-2).