| 摘要 |
PROBLEM TO BE SOLVED: To obtain a 2nd clock with sufficient S/N regardless of the restriction of S/N of a noise floor by a clock generation system which inputs a 1st clock, generates a 2nd clock of frequency in specific-ratio relation with the frequency of the 1st clock, and uses PLL circuits. SOLUTION: Multiple PLL circuits from an initial-stage PLL circuit 10a to which the 1st clock F1 is inputted to a final-stage PLL circuit 10c from which the 2nd clock F2 is outputted are cascaded and the 2nd clock F2 of frequency in specific-ratio relation with the frequency of the 1st clock F1 is generated. In this clock generation system, frequency division ratios are dispersed to frequency dividers of the respective PLL circuits and the frequency division ratios of the respective PLL circuits are so set that S/N's of at least the 2nd and succeeding PLL circuits are not determined by the S/N of the noise floor. |
