发明名称 Processor for processing variable length data
摘要 A processor, including a plurality of arithmetic and logic units for processing data for every bit in a word (W) unit, for processing variable length data, preferred for a communication oriented application, excellent in real time operability and a high speed processability, and capable of flexibly coping with changes in function, addition of functions, etc., provided with a processing mask control unit for dividing the data to be processed and data not to be processed, a carry mask control unit for controlling propagation of carry among the arithmetic and logic units, and a bit switch control unit for switching bits between two sets of data to be processed.
申请公布号 US2002124038(A1) 申请公布日期 2002.09.05
申请号 US20010817074 申请日期 2001.03.26
申请人 SAITOH MASAHIRO;TAKADA SYUJI;OOBA YASUHIRO 发明人 SAITOH MASAHIRO;TAKADA SYUJI;OOBA YASUHIRO
分类号 G06F7/50;G06F7/00;G06F7/38;G06F7/507;G06F7/57;G06F7/76;H04J3/16;H04J3/22;H04L12/56;(IPC1-7):G06F7/38 主分类号 G06F7/50
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