| 摘要 |
A double-bit non-volatile memory structure and a method of forming the structure. The main body of the structure is an array of double-bit memory cells partitioned out by mutually crossing isolation lines and bit lines. Each memory cell includes a pair of stacked gate structures, a doped region in between the stacked gate structures and a pair of common source/drain regions for the pair of stacked gate structures. Each control gate within the pair of stacked gate structures connects electrically with a neighboring word line and each source/drain region connects electrically with a bit line. To form the structure, a plurality of isolation lines is formed over a substrate and then a plurality of linear multi-layered structures perpendicular to the isolation lines are formed over the isolation lines. A pair of neighboring linear multi-layered structures forms a grid unit. Thereafter, source/drain regions and bit lines are formed between various grid units. A plurality of doped region is formed in the substrate in the middle of each grid unit. The linear multi-layered structures are patterned to form an array of stacked gate structures. Each pair of neighboring stacked gate structures forms a double-bit memory cell. Finally, words lines that are perpendicular to the bit lines are formed over the stacked gate structures.
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