发明名称 |
Testing apparatus and testing method for an integrated circuit, and integrated circuit |
摘要 |
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus comprises a pattern generator built in an integrated circuit to generate a test pattern, a plurality of shift registers configured with sequential circuit elements F/Fs inside the integrated circuit, and a pattern modifier modifying the test pattern generated by the pattern generator according to an external input, and inputting it to the plural shift registers. The apparatus is used as a testing apparatus for detecting manufacturing failure of an integrated circuit such as an LSI (Large Scale Integration) or the like.
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申请公布号 |
US2002124217(A1) |
申请公布日期 |
2002.09.05 |
申请号 |
US20010000089 |
申请日期 |
2001.12.04 |
申请人 |
FUJITSU LIMITED |
发明人 |
HIRAIDE TAKAHISA;YAMANAKA HITOSHI;KUMAGAI JUNKO;KONISHI HIDEAKI;MARUYAMA DAISUKE |
分类号 |
G01R31/28;G01R31/3181;G01R31/3183;G01R31/3185;G06F11/27;H01L21/66;H01L21/822;H01L27/04;(IPC1-7):G01R31/28;G06F11/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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