JTAG-based software to perform cumulative array repair

摘要

Repairing a plurality arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the plurality of arrays is selected for testing. Data patterns are sent from the on chip built in self test engine to the subset of the plurality of arrays on the processor at a plurality of operating parameters. A response is received at the on chip built in self test engine from the subset of the plurality of arrays at the plurality of operating parameters. The response from the subset of the plurality of arrays is compared to an expected response using the on chip built in self test engine, wherein the processor controller determines if additional test failures were detected by the ABIST engine(s) for the subset of the plurality of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.