Reducing power consumption by estimating load and reducing clock speed

摘要

A computer system has at least one processor (50) and at least one queue (65,66) for storing instructions for execution by the processor. By means of a clock estimation device (75) and associated clock (55), the processor is capable of being clocked at a plurality of rates. The number of instructions in the queue (65) is measured. The optimum clock rate is then selected based at least in part on the determined number of queued instructions. The clock estimation device (75) may also take into account the temperature of the processor (50), as measured by a temperature monitor (70), and the types of instructions that are queued.