Digital dual-loop DLL design using coarse and fine loops

摘要

A dual-loop digital delay locked loop (DLL) is provided. The DLL includes a coarse loop to produce a first delayed signal and provides a wide frequency lock range. The DLL further includes a fine loop connected to the coarse loop to produce a second delayed signal and provides a tight locking. This dual-loop architecture can provide robust operation and tight synchronization over a wide range of delay variations.