| 摘要 |
A memory device having an array of memory cells distributed into rows and columns with a plurality of interconnects extending across the array and coupled to carry write data during a first period of time and control data during a second period of time. In some embodiments where data I/O pads, input buffers, I/O sense amplifiers, write drivers, and color registers are collectively located on an opposite side of the array away from column decoders, column pre-decoders and column redundancy circuits, time-sharing of write data and control data on a single bus significantly improves layout efficiency.
|
