Programmable digital phase lock loop

摘要

A programmable digital phase lock loop produces an output bit clock signal that is synchronized to the rising edge of a reference input signal. In the absence of the reference input signal the programmable digital phase lock loop free runs creating an output bit clock signal at a programmed frequency. Various parameters of the output bit clock signal are programmable including its period, its offset from the reference input signal and its pulse width. There is provided an adjustment in the bit clock signal in the event that the required period thereof is not an integral multiple of the base clock signal of the programmable digital phase lock loop. The adjustment occurs only in the absence of the input reference signal. When the input reference signal is present its rising edge resynchronizes the output bit clock signal to the required frequency.