| 摘要 |
Circuitry for adding a first binary number (A) having a plurality of bits (a0, a1, . . . ) to a second binary number (B) having a plurality of bits (b0, b1, . . . ) to produce a third binary number (A+B) having a plurality of bits (s0, s1, . . . ) and/or a fourth binary number (A+B+1) having a plurality of bits (s0', s1', . . . ) and corresponding to the addition of the third binary number and one. The circuitry includes a plurality of stages wherein each stage has a first input for receiving a bit (ai) of the first binary number (A), a second input for receiving a bit (bi) of the second binary number (B) having the same binary weight (i) as the bit received at the first input and output means for producing a bit (si) of the third binary number (A+B) and/or a bit (s'i) of the fourth binary number (A+B+1), wherein said output means comprises exclusive OR means for combining a first signal and a second signal to produce a bit of the third binary number and the first signal and a third signal to produce a bit of the fourth binary number wherein said third signal is equivalent to said second signal if both the bits received at the first and second inputs have a LOW logic value, or for any stage having a lower binary weight, both the bits received at the first and second inputs have a LOW logic value and is otherwise equivalent to a predetermined logic value.
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