Simplified process for defining the tunnel area in non-aligned, non-volatile semiconductor memory cells

摘要

A simplified non-DSCP process for the definition of the tunnel area in nonvolatile memory cells with semi-conductor floating gates is presented. The memory cells are non-aligned and are incorporated in a matrix of cells and have associated control circuitry. In additional, to each cell a selection transistor is associated. The process includes at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semiconductor; and growth of tunnel oxide. Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.