发明名称 METHOD FOR ALLOCATING CLOCK TIMING
摘要 <p>PROBLEM TO BE SOLVED: To reduce the maximum value of current caused to flow to a circuit. SOLUTION: In a process S1, the path delay time of each path existing between two synchronous elements is calculated, and in a process S2, a signal change period and signal change cost are calculated between the two respective synchronous elements where paths exist. In a process S3, the signal change costs of the entire circuit to be a timing allocation object are added to calculate a synchronous change path cost sum, and in a process S4, the maximum value of the synchronous change path cost sum is calculated as a maximum synchronous path cost sum. In a process S5, whether or not the maximum synchronous change path cost sum, etc., satisfies an end condition is decided. When the maximum synchronous change path cost sum, etc., does not satisfy the end condition, in a process S6, clock timing to be allocated to a synchronous element of a timing allocation object is changed within the range of such a restriction with which a circuit including the synchronous element normally operates in a prescribed clock cycle so as to make a maximum synchronous change path cost sum to be minimum.</p>
申请公布号 JP2002245110(A) 申请公布日期 2002.08.30
申请号 JP20010042287 申请日期 2001.02.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MATSUMURA YOICHI;KUROKAWA KEIICHI;YASUI TAKUYA;TOYONAGA MASAHIKO
分类号 G06F17/50;G06F1/10;(IPC1-7):G06F17/50 主分类号 G06F17/50
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