发明名称 REDUNDANT LOGIC CIRCUIT HAVING DEVICE CHARGED MODEL ESD BREAKDOWN PROTECTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a device charged model ESD breakdown protecting redundant logic circuit wherein a redundant logic transistor can be surely protected to electrostatic discharge of a device charged model. SOLUTION: In the case that an electronic device which mounts the device charged model ESD breakdown protecting redundant logic circuit is subjected to electrostatic discharge of the device charged model, a diode 13 is inserted between a gate and a source of a P-type MOS transistor 11, and a diode 14 is inserted between a gate and a source of an N-type MOS transistor 12. Consequently, potentials of the gate terminals and the source terminals of the respective transistors are charged to the same potential instantaneously, and constitution for preventing electrostatic breakdown which is to be caused by the potential difference between the gate and the source is obtained.
申请公布号 JP2002246555(A) 申请公布日期 2002.08.30
申请号 JP20010041568 申请日期 2001.02.19
申请人 SEIKO INSTRUMENTS INC 发明人 ISHII TOSHIKI
分类号 H01L27/04;H01L21/822;H01L21/8238;H01L27/092;(IPC1-7):H01L27/04;H01L21/823 主分类号 H01L27/04
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