发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein high precision can be simply and effectively realized when a viahole is formed for connecting a lower wiring layer connected with a lower electrode layer of a capacitance element of an MIMC structure with an upper wiring layer. SOLUTION: A TiN layer 18, a Ta2O5 layer 20 and a TiN layer 22 which are turned into a lower electrode, a dielectrics layer and an upper electrode of the capacitance element later, respectively, are deposited on a first lower wiring layer 12a via an SiO2 interlayer insulating film 14, and a TiN/Ta2O5/TiN laminated layer 24 is formed. After that, photoresist is spread on the whole surface of base substance by using a photolithography technique. Irradiation of an exposure light whose wavelength is 193 nm (ArF) is performed, and a resist pattern 28 wherein an aperture 26a for a viahole whose diameter is 0.2-2.0μm is formed is formed above the first lower wiring layer 12a. At this time, the TiN/Ta2O5/TiN laminated layer 24 is made to act as a reflection protecting film whose reflectance for the exposure light is less than 10%.
申请公布号 JP2002246558(A) 申请公布日期 2002.08.30
申请号 JP20010042966 申请日期 2001.02.20
申请人 SONY CORP 发明人 EJIRI YOICHI
分类号 H01L21/3205;H01L21/027;H01L21/768;H01L21/822;H01L23/52;H01L23/522;H01L27/04;(IPC1-7):H01L27/04;H01L21/320 主分类号 H01L21/3205
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